Alibaba RISC-V CPU Runs Qwen 27B at 30 Tokens Per Second

Alibaba’s XuanTie C950 RISC-V CPU has reportedly run the Qwen-3.8 27B model at 30 tokens per second, per a Reddit post in r/LocalLLaMA. This is a single data point, but it indicates that open-standard RISC-V silicon can sustain interactive inference workloads, not just embedded tasks.

If reproducible, this shifts the infrastructure cost curve. ARM and x86 license and power overheads become negotiable, not fixed. For operators, a credible RISC-V path means procurement leverage against incumbent CPU vendors and a hedge against instruction-set lock-in. Practical effect: builders may soon benchmark inference on RISC-V clusters for low-power, high-density serving, particularly for mid-sized models like 27B that fit in a single node. The second-order effect is toolchain maturation—if kernels and runtimes optimize for RISC-V vector extensions, porting effort drops, and legacy x86-only optimization becomes less defensible. Workflow change: for edge or on-prem deployments, your bottleneck shifts from CPU availability to software compatibility. Validate the claim via your own benchmark before re-architecting.